An efﬁcient FPGA-based dynamic partial reconﬁguration design ﬂow and environment for image and signal processing IP cores - Krill, B. (Elsevier Ltd., 2010)
This paper describes a dynamic partial reconﬁguration (DPR) design ﬂow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design ﬂow, important features such as overall ﬂexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design ﬂow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design ﬂow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the ﬁeld programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconﬁguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efﬁcient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconﬁgurable areas is also presented in this paper.