Fujiwara, H., Iwata, H., Yoneda, T., & Ooi, C. Y. (2008). A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models. Institute of Electrical and Electronics Engineers.
Chicago Style CitationFujiwara, Hideo, Hiroyuki Iwata, Tomokazu Yoneda, and Chia Yee Ooi. A Nonscan Design-for-testability Method for Register-transfer-level Circuits to Guarantee Linear-depth Time Expansion Models. Institute of Electrical and Electronics Engineers, 2008.
MLA CitationFujiwara, Hideo, Hiroyuki Iwata, Tomokazu Yoneda, and Chia Yee Ooi. A Nonscan Design-for-testability Method for Register-transfer-level Circuits to Guarantee Linear-depth Time Expansion Models. Institute of Electrical and Electronics Engineers, 2008.