Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor - Saad, Ismail (American Institute of Physics, 2009)
Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGM-DP indicates a reasonable value of threshold voltage (V(T)), drive and off -leakage current (ION and I(OFF)), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current I(Dsat) due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously.