Husin, N. S., & Hani , M. K. (2008). Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design. Penerbit UTM.
Chicago Style CitationHusin, Nasir Shaikh, and Mohamed Khalil Hani. Simultaneous Routing and Buffer Insertion Algorithm for Minimizing Interconnect Delay in VLSI Layout Design. Penerbit UTM, 2008.
MLA CitationHusin, Nasir Shaikh, and Mohamed Khalil Hani. Simultaneous Routing and Buffer Insertion Algorithm for Minimizing Interconnect Delay in VLSI Layout Design. Penerbit UTM, 2008.
Warning: These citations may not always be 100% accurate.