An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
—In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnet...
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| Main Authors: | , , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2016
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/1/PDGC16%281%29.pdf |
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