Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using...
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| தலைமை எழà¯à®¤à¯à®¤à®¾à®³à®°à¯à®•ளà¯: | , , |
|---|---|
| வடிவமà¯: | Conference or Workshop Item |
| மொழி: | English |
| வெளியீடபà¯à®ªà®Ÿà¯à®Ÿà®¤à¯: |
2006
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| பகà¯à®¤à®¿à®•ளà¯: | |
| நிகழà¯à®¨à®¿à®²à¯ˆ அணà¯à®•லà¯: | http://irep.iium.edu.my/8227/ http://irep.iium.edu.my/8227/ http://irep.iium.edu.my/8227/1/ICECE_2006.pdf |
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