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Fabrikasi dan pencirian teknologi 0.13 um nMOS

The objective of this project is to design and simulate an nMOS transistor with a channel size of o. I 3 )lm. Implementing the scaling law, nMOS transistor o. 13 )lm is designed from a CMOS transistor 0.18 )lm recipe that had been designed and simulated previously using the same method. Some importa...

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தலைமை எழுத்தாளர்: Ahmad, Afandi
வடிவம்: Thesis
வெளியீடப்பட்டது: 2003
பகுதிகள்:
TK7800-8360 Electronics
நிகழ்நிலை அணுகல்:http://eprints.uthm.edu.my/1121/
http://eprints.uthm.edu.my/1121/1/24_Pages_from_FABRIKASI_DAN_PENCIRIAN_TEKNOLOGI_0.13um_NMOS.pdf
குறியீடுகள்: குறிச்சொல் இணை
குறியீடுகள் இல்லை, இந்த குறிச்சொல்லை முதலில் பதிவு செய்யுங்கள்!
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தொகுப்பு:The objective of this project is to design and simulate an nMOS transistor with a channel size of o. I 3 )lm. Implementing the scaling law, nMOS transistor o. 13 )lm is designed from a CMOS transistor 0.18 )lm recipe that had been designed and simulated previously using the same method. Some important parameters such as channel size, gate oxide thickness, ion implanted for voltage threshold modification had to be adjusted in searching the project goals. Fabrication and simulation is done using Virtual Wafer Fabrication (VWF) software by Silvaco Inc. TCAD Tools. Two primary tools are used during this project, which are ATHENA and ATLAS. ATHENA works as a simulation tool for the device fabrication process and ATLAS for electrical characteristics simulation. The simulation results are given in two-dimensional display using TONYPLOT editor. From this study, the value of threshold voltage (VTH) for nMOS transistor is 0.23503 V, junction depth (X}) is O. 198707 )lm; and the value of polysilicon sheet resistance is 8.63937 ohm/square. As a conclusion, the objective of this project is achieved. The tools of ATHENA and ATLAS and the scaling factor (5) = 1.38 are relevant.

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