Electromagnetic emission and reduction of digital circuits with various clock frequencies
Most digital electronic products must comply with the Electromagnetic Compatibility (EMC) requirements to access the market of EMC-enforced countries. One of the EMC requirements is to control unwanted emission of electromagnetic (EM) energy. However, as the clock frequency goes higher, it is a grea...
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| Format: | Thesis |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/2421/ http://eprints.uthm.edu.my/2421/1/Saizalmursidi.pdf |
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| Summary: | Most digital electronic products must comply with the Electromagnetic
Compatibility (EMC) requirements to access the market of EMC-enforced countries.
One of the EMC requirements is to control unwanted emission of electromagnetic
(EM) energy. However, as the clock frequency goes higher, it is a greater challenge
to design EMC-complied circuitry due to the problem of rahation in the harmonic
frequencies. Consequently, it is crucial to understand the basic concepts of the
emission mechanisms and the suitable mitigation techniques to ensure EMC
compliance. This research was to characterise the sources of radiated emissions from
a hgital circuit and investigate the effects of employing EMC design practices on the
reduction of emission. The novelty of this research is athibuted to the
comprehensive study on the sources of emission and mitigation techniques of digital
circuits on double-sided board at 0.125 MHz, 0.25 MHz, 1.25 MHz, 2.5 MHz, 12.5
MHz and 25 MHz. The radiated emissions are measured for various mitigation
techmques such as the size of loop area, length of cable and signal currents. The
measurement results are then compared with the radiated emission limits of
European Norm (EN) 55022 and the Federal Communications Commission (FCC)
Part 15 Class B. Nine Printed Circuit Board (PCB) layouts with different design are
designed and fabricated by using the IsoPro software and the Quick Circuit milling
machine. The peak measurements were conducted in a 3-meter Semi Anechoic
Chamber (SAC) in the frequency range from 30 MHz to 1 GHz. The results showed
a reduction of emission level by an average 6.5 dB at frequency below 800 MHz
(harmonics) by keeping the loop of return current small. However, the emission
level for harmonic frequencies of 25 MHz or 12.5 MHz clock signals increase above
the frequency of 300 MHz. Series resistor on each signal trace reduces the level by
an average 10 dB above the frequency 175 MHz to 1 GHz. The employment of
small area of ground plane for critical clock trace routing and wide power trace can
reduce the emission by an average of about 9.1 dB. |
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