Implementation of adiabatic dynamic logic in bit full adder
Very large scale integrated circuit (VLSI) is the technology of designing many thousands of semiconductor devices on a single chip with the small of power dissipation. However, the power dissipation still becomes a critical concern in most digital CMOS circuits. The main part of the power dissipatio...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
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| Online Access: | http://eprints.uthm.edu.my/2740/ http://eprints.uthm.edu.my/2740/1/ELE_16I.pdf |
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| Summary: | Very large scale integrated circuit (VLSI) is the
technology of designing many thousands of semiconductor
devices on a single chip with the small of power dissipation.
However, the power dissipation still becomes a critical
concern in most digital CMOS circuits. The main part of the
power dissipation is caused by the capacitive signal nodes
are rapidly charged and discharge through MOS devices.
Continuing to improve the performance and integrating
more function into each chip, feature size has to continue to
shrink. As the result, the magnitude of power per unit area
increases. Adiabatic Dynamic Logic is referred to as the
energy recovery technique. The energy used to charge the
capacitive signal nodes in a circuit may be recovered during
discharge and stored for recycle. The main advantage of this
technique is to reduce the power dissipation in the CMOS
circuits. In this paper, the logic gates such like Inveter, Nand
Nor and 1 Bit Full Adder had been designed by
implementing the adiabatic dynamic technique. As the
results, the count of transistors had been found reduced
about 50 percent and the power consumed in the adiabatic
dynamic 1 bit adder is 3.23x10-26 Watts compared to
conventional technique which consumed about 233x10-12
Watts. This showed that the technique could reduce the
power dissipation more than 90%. The circuits were
designed using a 1.2μm technology of CMOS process and
the performance had been tested at frequency of 27 MHz. |
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