Efficient architectures for 3D HWT using dynamic partial reconfiguration
This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the prop...
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| Main Authors: | , , |
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| Format: | Article |
| Published: |
Elsevier Ltd.
2010
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/3046/ |
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| Summary: | This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform
(HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field
programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the
proposed architecture has been implemented using a cascade of three N-point one dimensional (1D)
HWT and two transpose memories for a 3D volume of N � N � N suitable for real-time 3D medical imaging applications. These applications require continuous hardware servicing, hence DPR has been introduced. Two architectures were synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs.
Experimental results and comparisons between different configurations using partial and non-partial
reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are analysed in this paper. |
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