Simulation study on NMOS gate length variation using TCAD tool
The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predic...
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| Main Authors: | , , , |
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| Format: | Article |
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| Online Access: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5206255 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5206255 |
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