Simulation, fabrication and characterization of PMOS transistor device
In a low supply voltage CMOS technology, it is desirable to scale threshold voltage and gate length for improving circuit performance. Therefore, a project has been carried out inside KUiTTHO's microelectronic cleanroom to produce a method that has better l ow power/low voltage current concentr...
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| Format: | Thesis |
| Published: |
2006
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/813/ http://eprints.uthm.edu.my/813/1/24_Pages_from_SIMULATION%2C_FABRICATION_AND_CHARACTERIZATION_OF_PMOS_TRANSISTOR_DEVICE.pdf |
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| Summary: | In a low supply voltage CMOS technology, it is desirable to scale threshold
voltage and gate length for improving circuit performance. Therefore, a project has been
carried out inside KUiTTHO's microelectronic cleanroom to produce a method that has
better l ow power/low voltage current concentrate on p-channel (PMOS). An experiment
was also done to determine the right parameter value to b e used for fabrication process
such as oxidation process thickness rate, sheet resistance and metal thickness. From the
parameter value obtained, 0.3 m m and 0.5 mm PMOS transistor had been successfully
produced. Fabrication simulation was performed to produce a 0.1 |am and 0.3p.m PMOS
transistor by using the ISE-TCAD software. The trade off between threshold voltage
(VTH), gate length (LG) and thin oxide thickness (tox) are discussed to determine the
characteristics of the transistors. It shows that for 0.3mm (toX = 860A) PMOS transistor
the value of VT H =-3.33V and 0.5 mm ( t ^ = 910A), VT H value =-4.3V. From the
simulation result show for 0.1 jim (to* = 200A), VT H = - 0 . 3 1 4V and for 0 . 5 | im (400A)
Vt h = -0.634V. The result shows that, with decreasing gate length and oxide thickness
will produce lower value of threshold voltage. Minimum value of threshold voltage can
result in a better performance of transistor. Another parameter must be taken into
consideration such as leakage current, resistivity and conductivity to get a better design
of PMOS transistor in future research. |
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