Interconnect tree optimization algorithm in nanometer very large scale integration designs
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant f...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/9178/ http://eprints.uthm.edu.my/9178/1/Chessda_Uttraphan_Eh_Kan.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|