Interconnect tree optimization algorithm in nanometer very large scale integration designs
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant f...
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| 格式: | Thesis |
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2016
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| 在线阅读: | http://eprints.uthm.edu.my/9178/ http://eprints.uthm.edu.my/9178/1/Chessda_Uttraphan_Eh_Kan.pdf |
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