Description: Electronic system level (ESL) design methodology for IP-based system-on-chip (SoC)

Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns.

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Bibliographic Details
Main Authors:	Khalil-Hani, Mohamed, Ahmad, llliasaak, Hau, Yuan
Format:	Conference or Workshop Item
Published:	2007
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/13949/
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Description
Summary:	Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns.