100 MS/s, 10-bit ADC using pipelined successive approximation
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined...
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| Main Authors: | , , , , |
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| 格式: | Article |
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World Scientific Publication
2014
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| 在线阅读: | http://eprints.utm.my/51428/ http://eprints.utm.my/51428/ http://eprints.utm.my/51428/ |
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