Low latency Network-on-Chip router microarchitecture using request masking technique
Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An ef...
Disimpan dalam:
| Pengarang-pengarang Utama: | , , |
|---|---|
| Format: | Artikel |
| Diterbitkan: |
2015
|
| Subjek-subjek: | |
| Capaian Atas Talian: | http://eprints.utm.my/58488/ http://eprints.utm.my/58488/ |
| Penanda-penanda: |
Tambah Penanda
Tiada Penanda, Jadilah orang pertama menanda rekod ini!
|
Jadilah orang pertama meninggalkan komen!