The implementation of a pipelined floating-point CORDIC coprocessor on NIOS II soft processor
This paper discusses the implementation of a pipelined floating-point Coordinate Rotation Digital Computer (CORDIC) coprocessor using Field Programmable Gate Array (FPGA) to accelerate the computation speed in solving elementary functions on NIOS II soft processor. Examples of the elementary functio...
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| Pengarang-pengarang Utama: | , , , |
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| Format: | Conference or Workshop Item |
| Diterbitkan: |
2015
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| Subjek-subjek: | |
| Capaian Atas Talian: | http://eprints.utm.my/60606/ http://eprints.utm.my/60606/ |
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