Phonon scattering effects in drain-current model of carbon nanotube and silicon nanowire field-effect transistors
Carbon nanotubes (CNTs) and silicon nanowires (Si NWs) are the potential candidate for the channel material in the next generation of transistors. Although previous works have shown that both CNT- and Si NW-based field-effect-transistors (FET) are able to deliver better performance than conventional...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Published: |
American Scientific Publishers
2016
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/71271/ http://eprints.utm.my/71271/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Carbon nanotubes (CNTs) and silicon nanowires (Si NWs) are the potential candidate for the channel material in the next generation of transistors. Although previous works have shown that both CNT- and Si NW-based field-effect-transistors (FET) are able to deliver better performance than conventional devices, phonon scattering occurs. In this paper, we examine the phonon scattering effects on the electrical transport characteristic of CNTFETs and Si NWFETs. The impact of phonon scattering is incorporated into the devices through the transmission probability into the ballistic current equation. There are two types of phonons, acoustic phonons and optical phonons, with different mean free paths (MFP). The results show that the effective MFP follows the acoustic phonon MFP at a low gate bias and switches to the optical phonon MFP at a high gate bias. The acoustic phonon is the primary cause of current reduction at a low gate bias, while the optical phonon is dominant in reducing the current at a high gate bias. The ballisticity, which is the ratio of the scattering current to the ballistic current at different channel lengths is examined. It is revealed that transistors with a shorter length operate close to the ballistic region, which is expected, as they approach the phonon MFP. Performances metrics such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and on-off ratio at different channel length are calculated. The potential of CNTFETs and Si NWFETs work as logic gates are determined through the voltage transfer characteristic (VTC). Finally, the accuracy of the simulation results is verified by comparing with published models and experimental data, exhibiting good agreement with both data. |
|---|