Topology of 2 input subnanowatt XOR gate in 65nm CMOS technology
Exclusive OR (XOR) gate is highly utilized in various digital system applications such as full adder, comparator, parity generator and encryption processor, which leads to increased in the interests to enhance the performance of XOR gate. A novel design of low power and high performance XOR gate usi...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
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| Online Access: | http://eprints.uthm.edu.my/3356/ http://eprints.uthm.edu.my/3356/1/140._1569636579.pdf |
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| Summary: | Exclusive OR (XOR) gate is highly utilized in various
digital system applications such as full adder, comparator, parity generator and encryption processor, which leads to increased in the interests to enhance the performance of XOR gate. A novel design of low power and high performance XOR gate using six transistors application are proposed in this paper. The new XOR gate has been compared with previous design in term of power,delay and power-delay product (PDP). The XOR gate is simulated using Cadence Spectre with 65nm Complementary Metal Oxide Semiconductor (CMOS) technology at different supply voltages with a range of 0.6V to 1.2V. The area of the core circuit is approximately 48 μm2. The critical path propagation delay is 1.585 ns with power dissipation of only around 3.256 fW at 0.8V supply voltage .The results demonstrate that the proposed design
achieve a lowest power consumption and high speed with respect to other designs. |
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