An AES tightly coupled hardware accelerator in an FPGA-based Embedded processor core
This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system...
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| Main Authors: | , , |
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| Format: | Book Section |
| Published: |
IEEE Explore
2009
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| Subjects: | |
| Online Access: | http://eprints.utm.my/12962/ http://eprints.utm.my/12962/ http://eprints.utm.my/12962/ |
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