Structure design challenge in nano-cmos device.
This paper intends to report the problems and challenges that lie ahead in transistor design methodology in nano-CMOS structure. Thus, it is desired to see the options in improving the device design on top of continuing the scaling process of transistor in the next few years to come. The main concer...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2008
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/2259/ http://eprints.uthm.edu.my/2259/1/Structure_design_challenge.pdf |
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| Summary: | This paper intends to report the problems and
challenges that lie ahead in transistor design
methodology in nano-CMOS structure. Thus, it is
desired to see the options in improving the device
design on top of continuing the scaling process of
transistor in the next few years to come. The main
concern is to see how the transistors behave as the
size of device shrinks down to below 100nm range.
Besides, the demand of future generations is
expected as a result of more compact of digital
circuit. It is concluded that although several
problems surfaces as the transistor enters the nano-
CMOS era, there are excellent options to solve those
problems and thus could help to reduce the
transistor size and yet uncompromised the device
performance. |
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