FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration
This paper presents a combination of novel feature vectors construction approach for face recognitionusing discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four ex...
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| வெளியீடபà¯à®ªà®Ÿà¯à®Ÿà®¤à¯: |
Springer-Verlag
2011
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| பகà¯à®¤à®¿à®•à®³à¯: | |
| நிகழà¯à®¨à®¿à®²à¯ˆ அணà¯à®•à®²à¯: | http://dx.doi.org/10.1007/s11554-011-0221-x http://dx.doi.org/10.1007/s11554-011-0221-x http://eprints.uthm.edu.my/3862/1/afandi_ahmad_2_U.pdf |
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