IDD scan test method for fault localization technique on CMOS VLSI failure analysis
One of the fashionable stress test has been practice on CMOS VLSI recently known as IDDQ scan test. It have competency to be as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on log...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
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| Online Access: | http://eprints.uthm.edu.my/3017/ |
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