A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models
This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the tk notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclica...
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| Pengarang-pengarang Utama: | , , , |
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| Format: | Artikel |
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Institute of Electrical and Electronics Engineers
2008
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| Capaian Atas Talian: | http://eprints.utm.my/12802/ http://eprints.utm.my/12802/ http://eprints.utm.my/12802/ |
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| Ringkasan: | This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the tk notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake et al Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing. |
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