A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models
This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the tk notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclica...
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| Main Authors: | , , , |
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| Format: | Article |
| Published: |
Institute of Electrical and Electronics Engineers
2008
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| Subjects: | |
| Online Access: | http://eprints.utm.my/12802/ http://eprints.utm.my/12802/ http://eprints.utm.my/12802/ |
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